Xilinx XC6SLX25 Spartan-6 user FPGA accessible on Local Address/DataBus; PCI to Local Bus Interface is handled by the PCI Target Chip; Programmable EEPROM for PCI Configuration Space Parameters; In-System-Programmable SPI Flash for User FPGA Configuration; User FPGA directly In-System-Programmable by Software; Baud Rate Oscillator available at User FPGA Pin; I/O options: 64 TTL I/O (-10R), 32 differential I/O RS422/485 (-11R), 32 TTL I/O and 16 diff. I/O RS422/485 (-12R), 32 differential I/O M-LVDS (-13R), 32 TTL I/O and 16 diff. I/O M-LVDS (-14R); I/O lines accessible on both HD68 Front Connector and  P14 Rear Connector; Operating temperature: -40°C to +85°C