TPMC644

Re-Configurable FPGA with 64 TTL I/O / 32 Diff. I/O

Standard single-width PMC module
User configurable FPGA (AMD Spartan™ 7)
64 TTL I/O lines or 32 differential I/O lines (EIA-422 / EIA485) or 32 differential I/O lines (M-LVDS) or 32 TTL I/O lines and 16 differential I/O lines
I/O direction is individually programmable
Configurable pull voltage for TTL I/O
On board termination resistors for differential I/O
Auto-configurable User FPGA
User FPGA and SPI Flash are in-system programmable via PCI bus
User FPGA JTAG port via on-board header

Product status: Active

Operating Temperature Range -40 °C to +85 °C

The TPMC644 is a standard single-width PMC module providing a user configurable AMD Spartan™ 7 FPGA (XC7S50) and up to 64 single-ended TTL compatible I/O lines or up to 32 differential I/O lines.

All I/O lines are individually programmable as input or output.

Each TTL I/O line has an on-board pull resistor to a common/shared reference. The pull resistor reference is configurable to 3.3 V, 5 V or GND. The differential I/O lines have on-board termination resistors.

The User FPGA is auto-configurable by an on-board SPI Flash. Both the User FPGA and the SPI Flash for User FPGA configuration are in-system-programmable via the PCI bus. An on-board JTAG header provides access to the user FPGA JTAG port.

PCI configuration space parameters are configurable by an on-board serial EEPROM.

TEWS Technologies is a partner at the highest level within the AMD Embedded Partner Program and offers FPGA Design and Integration services for all its FPGA solutions. The engineering team specializes in designing highly optimized FPGA designs and has extensive experience in minimizing FPGA gate usage. Having the FPGA custom designed according to the customer’s needs avoids overhead and delays leading to a reduction of costs for the customer.

Learn more about TEWS Technologies FPGA Development capabilities.

Mechanical Interface

PCI Mezzanine Card (PMC) conforming to IEEE P1386/P1386.1 Standard/Short Single-Width (149 mm x 74 mm)

Electrical Interface

PCI Rev. 3.0 compatible 33 MHz / 32 bit PCI
3.3 V and 5 V PCI Signaling Voltage compatible

User FPGA

AMD Spartan™ 7 (XC7S50)

Front I/O Channels

-10R	64x 3.3 V LVTTL I/O, 5 V tolerant, Common Pull-Option.
-11R	32x RS485 I/O, On-Board 120 Ω Line Termination.
-12R	16x RS485 I/O, On-Board 120 Ω Line Termination, 32x 3.3 V LVTTL I/O. 5 V tolerant.
-13R	32x M-LVDS I/O, On-Board 100 Ω Line Termination.
-14R	16x M-LVDS I/O, On-Board 100 Ω Line Termination, 32x 3.3 V LVTTL I/O. 5 V tolerant.

Rear I/O Channels

32 + 2 Dedicated Direct FPGA I/O lines (unprotected)

Power Requirements ¹⁾

Depends on FPGA design
900 mA typical @ +5 V DC

Temperature Range

Operating: -40 °C to +85 °C (Adequate forced air cooling is required)
Storage: -40 °C to +125 °C

MTBF ¹⁾

441000 h to 496000 h

Humidity

5% – 95% non-condensing

Weight

115 g (including Heatsink)

¹⁾ depends on variant, for further details see User Manual

PRODUCT VARIATIONS

TPMC644-10R	Re-Configurable FPGA with 64 TTL I/O The TPMC644-10R provides 64 ESD-protected TTL (LVTTL) lines.
TPMC644-11R	Re-Configurable FPGA with 32 Differential EIA- 422 / EIA-485 I/O The TPMC644-11R provides 32 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers.
TPMC644-12R	Re-Configurable FPGA with 16 Differential EIA- 422 / EIA-485 I/O and 32 TTL I/O The TPMC644-12R provides a mix of 32 TTL (LVTTL) and 16 differential RS422/485 I/O lines.
TPMC644-13R	Re-Configurable FPGA with 32 Differential M-LVDS I/O The TPMC644-13R provides 32 differential I/O lines using M-LVDS line transceivers.
TPMC644-14R	Re-Configurable FPGA with 16 Differential MLVDS I/O and 32 TTL I/O The TPMC644-14R provides a mix of 32 TTL (LVTTL) and 16 differential M-LVDS I/O lines.

ACCESSORIES

TA304

Cable Kit for Modules with HD68 / SCSI-3 Connector

SOFTWARE

TDRV018-SW

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet

Data Sheet - Issue 1.0.0

User Manual

User Manual - Issue 1.0.0