TPCE210 | PCI Express x4, Gen 2, Dual QMC Carrier

VITA 93 – QMC

THE NEXT GeNERATION Flexible Mezzanine Concept

The new VITA 93 – QMC standard addresses the inherent challenges in current mezzanine card standards through its innovative QMC architecture, enabling unprecedented modularity, flexibility, and scalability while maintaining backward compatibility and rugged reliability. VITA 93 – QMC builds on lessons learned from previous standards, blending their best features with new capabilities for the future.

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MORE THAN 40 YEARS OF EXPERIENCE

Customer first approach

Using this customer first approach, TEWS has developed a large number of standard and custom products for applications in industrial control, telecommunication infrastructure, medical equipment, traffic control and COTS. TEWS line of embedded I/O solutions is available worldwide through a global network of distributors.

Featured Products

TCPS210 I CompactPCI-Serial Carrier with 3 QMC Sites, PCIe Gen3 x4, Rear-I/O

TCPS210

CompactPCI-Serial Carrier with 3 QMC Sites, PCIe Gen3 x4, Rear-I/O

  • CompactPCI-Serial compatible 3U module (PICMG CPCI-S.0 R3.0)
  • Cost-effective solution to provide I/O in CompactPCI-Serial environment
  • Flexible I/O (TEWS offers a wide range of QMCs)
  • 3 single-width QMC Sites, compatible with double- and triple-width QMCs
  • Full QMC I/O on P2, P3 an P4 rear I/O
  • PCIe Gen3 x4 from host to QMCs
  • Management controller for surveillance of QMC health status
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TQMC400 I 4 Channel Full-Modem RS232/RS422/RS485 Programmable Serial Interface QMC Module

TQMC400

4 Channel Full-Modem RS232/RS422/RS485 Programmable Serial Interface

  • Standard single QMC module conforming to VITA 93.0
  • 4 UART channels with programmable RS232 / RS422 / RS485 interfaces
  • High performance asynchronous serial interface (up to 20 Mbps)
  • Software selectable 120 Ω Termination for each RS422/RS485 channel
  • Hardware handshake support available
  • Half-duplex mode available
  • 256 byte FIFO
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TQMC600 I Reconfigurable FPGA with Digital I/O QMC Module

TQMC600

Reconfigurable FPGA with Digital I/O

  • Standard single-width QMC module conforming to VITA 93.0
  • User programmable FPGA
  • 32 TTL lines, 5 V tolerant or 16 differential I/O lines (EIA-422 / EIA-485 compatible) or 16 differential Multipoint-LVDS lines
  • ESD protected I/O lines
  • Each I/O line is individually configurable (e.g. direction)
  • 3 state TTL output (high, low, and tristate)
  • Onboard termination for differential I/O lines
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TQMC801 I QMC Module with 1 Channel 1000BASE-KX Ethernet

TQMC801

1000BASE-KX Ethernet

  • Standard single-width QMC module conforming to VITA 93.0
  • 1000BASE-KX Ethernet
  • PXE and iSCSI boot (16 Mbit serial flash)
  • IEEE 1588/802.1AS Precision Time Protocol (PTP)
  • IEEE 802.1Qav Audio/Video Bridging (AVB) traffic shaping
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TPMC151 | 4 Channel Resolver/LVDT-to-Digital Converter

TPMC151

4 Channel Resolver/LVDT-to-Digital Converter

  • Standard single-width 32 bit PMC module
  • 4 channels Resolver or LVDT/RVDT-to-digital converter, option for 2 synchro channels available
  • 16 bit resolution
  • 0-12 VRMS programmable input
  • 0-12 VRMS, 1-20 kHz programmable excitation
  • Tracking rate up to ¼ excitation frequency
  • Angle and velocity output
  • Front panel I/O (50-pin MDR type connector)
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TXMC397 I Conduction Cooled 2 Channel 10GBASE-T Ethernet

TXMC397

Conduction Cooled, 2 Channel 10GBASE-T Ethernet

  • Conduction Cooled single-width XMC module
  • 2 channel 10GBASE-T / NBASE-T / 1000BASE-T / 100BASE-TX
  • IPMI resource: FRU hardware definition information stored in on-board EEPROM
  • PXE and iSCSI boot (64 Mbit serial flash)
  • IEEE 1588/802.1AS Precision Time Protocol (PTP)
  • Rear I/O via P16 – Both channels mapped in X12d range or both channels mapped in X8d range (VITA46.9)
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TXMC897

2 Channel 10GBASE-T and 2 Channel SFP+ 10 Gigabit Ethernet

  • Short single-width XMC module
  • 2 channel 10GBASE-T / NBASE-T / 1000BASE-T / 100BASE-TX and 2 channel SFP+ 10 Gigabit
  • IPMI resource: FRU hardware definition information stored in on-board EEPROM
  • PXE and iSCSI boot (64 Mbit serial flash)
  • IEEE 1588/802.1AS Precision Time Protocol (PTP)
  • Front I/O via 2 RJ45 connectors and 2 SFP+ connectors
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TXMC637_image

TXMC637

Reconfigurable FPGA with 32x Analog Input 8x Analog Output and 32x Digital I/O

  • Standard XMC Module
  • User configurable FPGA (AMD Artix™ 7)
  • DDR3 SDRAM bank, 256M x 16 bit (512 MB)
  • 32 channels 16 bit ADC
    • Offering single-ended and differential mode
    • Programmable input voltage
    • Conversion time: up to 1.1 µs
    • Sampling rate up to 1 Msps
  • 8 channels single-ended analog output
    • 16 bit resolution
    • Programmable output voltage: ±10 V, ±5.0 V or ±2.5 V
    • Full scale settling time: typ.1 µs
  • 32 digital TTL compatible I/O lines
    • 16 lines optional configurable as differential RS422 interface
  • P14/P16 Rear I/O lines
    • 64 single ended or 32 differential rear I/O lines on a rear XMC 64 pin P14 connector
    • 4 FPGA Multi-Gigabit-Transceiver on a rear XMC P16 connector
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TPMC543 I Analog Current & High-Voltage Input Channels, Analog Voltage/Current Output Channels and Digital LVTTL/TTL I/O Channels PMC Module

TPMC543

Analog Current & High-Voltage Input Channels, Analog Voltage/Current Output Channels and Digital LVTTL/TTL I/O Channels

  • Standard single-width PMC module
  • 8 differential bipolar analog current input channels
  • 16 (single-ended) or 8 (differential) bipolar analog high-voltage input channels
  • 8 analog output channels (single-ended, simultaneous update, bipolar & unipolar ranges)
  • 8 ESD protected digital LVTTL/TTL I/O channels
  • AD/DA DMA support
  • AD/DA Factory calibration data available via EEPROM
  • AD/DA Analog I/O hardware correction function available
  • External synchronization option via P14 I/O
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TPMC321 I Conduction cooled 64 Digital TTL I/O / 32 Differential I/O PMC Module

TPMC321

Conduction cooled 64 Digital TTL I/O / 32 Differential I/O

  • Conduction cooled single-width 32 bit PMC module
  • 64 Bit I/O – TTL signaling voltage level or 32 Differential Bit I/O – EIA-485 or 32 Differential Bit I/O – M-LVDS
  • ESD protection
  • Rear-IO via P14
  • Individually programmable I/O lines (direction, pullup/pulldown)
  • Input events can generated interrupts individually for each channel
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