Reconfigurable FPGA with 16x Analog Input 8x Analog Output and 32x Digital I/O

  • Standard XMC Module
  • User configurable FPGA (AMD Artix™ 7)
  • DDR3 SDRAM bank, 256M x 16 bit (512 MB)
  • 32 channels 16 bit ADC
    • Offering single-ended and differential mode
    • Programmable input voltage
    • Conversion time: up to 1.1 µs
    • Sampling rate up to 1 Msps
  • 8 channels single-ended analog output
    • 16 bit resolution
    • Programmable output voltage: ±10 V, ±5.0 V or ±2.5 V
    • Full scale settling time: typ.1 µs
  • 32 digital TTL compatible I/O lines
    • 16 lines optional configurable as differential RS422 interface
  • P14/P16 Rear I/O lines
    • 64 single ended or 32 differential rear I/O lines on a rear XMC 64 pin P14 connector
    • 4 FPGA Multi-Gigabit-Transceiver on a rear XMC P16 connector

Product status: Active

Operating Temperature Range -40 °C to +85 °C RoHS compliant

The TXMC637 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable FPGA (AMD Artix™ 7).

32 ADC input channels, based on four ADAS3022, can be software configured in groups to operate in single-ended or differential mode. Each of the 32 channels has a resolution of 16 bit and can work with up to 1 Msps. The programmable gain amplifier is software configurable and allows a full-scale input voltage range of up to +/-10.24V.

The TXMC637 DAC output channels are based on the Dual 16 bit AD5547 DAC. Each DAC output is designed as a configurable single-ended bipolar analog output. Output voltage is configurable as ±10.0V, ±5.0V or ±2.5V.

32 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programmable either as input or output. Input I/O lines are tri-stated and could be used with the on-board pull up or as tri-stated output. Each TTL I/O line has a pull resistor sourced by a common pull source. The pull voltage level is selectable to be either +3.3V, +5V and additionally GND.

16 of these ESD-protected TTL lines can be configured to be either a TTL interface or RS422 interface. Switching is done via the User FPGA. All 8 RS422 transceivers have individual internal switchable terminations.

The User FPGA is connected to a 512 Mbytes, 16 bit wide DDR3L SDRAM.  (to be used with the AMD Memory Interface Generator)

For customer specific I/O extension or inter-board communication, the TXMC637 provides 64 FPGA I/Os on P14 (directly connected) and 4 FPGA Multi-Gigabit-Transceivers on P16. All P14 I/O lines can be configured in accordance with 7-Series. Select I/O features e.g. as 64 single ended LVCMOS25 or as 32 differential LVDS25 interface.

The User FPGA is configured by a serial quad SPI flash. For full PCIe specification compliance, the AMD Tandem Configuration Feature can be required for FPGA configuration. AMD Tandem Methodologies “Tandem PROM” should be the favored Methodology. The SPI flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for (real-time) debugging of the FPGA design.

User applications for the TXMC637 with Artix™ 7 FPGA can be developed using the AMD Vivado™ design tool. TEWS offers a well-documented FPGA Board Reference Design. It includes a constraint file with all necessary pin assignments and basic timing constraints. The FPGA Board Reference Design covers the main functionalities of the board.

The TXMC637 is delivered with the FPGA Board Reference Design. The FPGA could be programmed via the on-board Board Configuration Controller (BCC). Programming via JTAG interface using an USB programmer is also possible. In accordance with the PCI specification and the buffering of PCI header data, the contents of the user FPGA can be changed during operation.

TEWS Technologies is an Elite Certified AMD Adaptive Computing Partner and offers FPGA Design and Integration services for all its FPGA solutions. The engineering team specializes in designing highly optimized FPGA designs and has extensive experience in minimizing FPGA gate usage. Having the FPGA custom designed according to the customer’s needs avoids overhead and delays leading to a reduction of costs for the customer.

AMD Adaptive Computing Partner Elite Certified

Learn more about TEWS Technologies FPGA Development capabilities. 

Mechanical Interface Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard)

Standard single-width (149mm x 74mm)

Electrical Interface PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer Standard)
PCI Express Switch PI7C9X2G312GP (Pericom)
PCI Express to PCI Bridge XIO2001 (Texas Instruments)
User configurable FPGA XC7A200T-2FBG676I (AMD)
SPI-Flash MT25QL128 (Micron) 128Mbit (contains TXMC637 FPGA BRD) or compatible; +3.3V supply voltage
DDR3 RAM 1 x MT41K256M16TW-107 (Micron) 256Meg x 16Bit
Board Configuration Controller LCMXO2-7000HC (Lattice)
ADC ADAS3022BCPZ -16 (Analog Devices)
DAC AD5547BRUZ (Analog Devices)
A/D Channels Input Configuration per ADC Device:

8x Single-Ended A/D Channels or 4x Differential A/D Channels


A/D Channel Input Range Options:

Single-Ended Input Voltage Ranges:

±0.64 V, ±1.28 V, ±2.56 V, ±5.12 V, ±10.24 V, ±12.228 V

Differential Input Voltage Ranges:

±0.64 V, ±1.28 V, ±2.56 V, ±5.12 V, ±10.24 V, ±20.48 V, ±24.576 V


On-board analog input 1st order low-pass filter with -3 dB cutoff frequency of approx. 105 kHz on all A/D channels
Max conversion Rate from 100 ksps to 800 ksps, depending on the number of active channels per ADC device.
Pseudo-Simultaneous conversion for all A/D channels

D/A Channels 8 Single-Ended 16 Bit D/A Channels

Output range configurable per D/A channel.
Simultaneous Conversion for all D/A Channels.


Maximum single-ended Output Voltage – Vout: ±10 V

Maximum Output Drive Current for each Output: 10 mA

Maximum Capacitive Load for each Output: 1000 pF

Typical Settling Time for a 10 mA / 1000 pF: < 1 µs

Digital Front I/O Channels 32 digital I/O Lines

·   Default configured as 32 ESD-protected TTL lines

·   16 I/O lines are configurable as 8 differential RS422 I/O lines with individual Termination enable.

Digital Rear I/O Channels 64 direct FPGA I/O lines to P14 Rear I/O connector

·  Can be used as single-ended or differential I/O

·  FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25


4 MGT lines to P16 Rear I/O connector

·  Each line consists of one differential RX and TX pair.

Transmission speeds of up to 3.125 Gb/s are possible.

Front I/O Front I/O Honda – HDRA-EC100LFDT-SL+
P14 Rear I/O 64 pin Mezzanine Connector (Molex 71436-2864 or compatible)
P16 Rear I/O 114 pin Mezzanine Connector (Samtec – ASP-105885-01)
Power Requirements 1) Depends on FPGA design

With TXMC637 Board Reference Design / without external load

typical @ +12 V VPWR typical @ +5 V VPWR
0.930 A 2.0 A
Temperature Range Operating: -40 °C to +85 °C
Storage: -55 °C to +125 °C
MTBF 170 000 h
Humidity 5% – 95% non-condensing
Weight 130 g



Reconfigurable FPGA with 16 x Analog Input 8 x Analog Output and 32 Digital I/O

AMD Artix™ 7 FPGA (XC7A200T-2FBG676I); 512 Mbytes DDR3; 16 Analog Input; 8 Analog Output; 32 Digital I/O; 64 direct FPGA Back I/O Lines on P14; 4 MGTs on P16


VHDCI-100 Cable, 1.2 m

HD50 / SCSI-2 Terminal Block


Device Driver for Board Family with Reconfigurable FPGA

Data Sheet

Data Sheet

Data Sheet - Issue 1.0.2

User Manual

User Manual - Issue 1.0.2