The TXMC637 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable FPGA (AMD Artix™ 7).
32 ADC input channels, based on four ADAS3022, can be software configured in groups to operate in single-ended or differential mode. Each of the 32 channels has a resolution of 16 bit and can work with up to 1 Msps. The programmable gain amplifier is software configurable and allows a full-scale input voltage range of up to +/-10.24V.
The TXMC637 DAC output channels are based on the Dual 16 bit AD5547 DAC. Each DAC output is designed as a configurable single-ended bipolar analog output. Output voltage is configurable as ±10.0V, ±5.0V or ±2.5V.
32 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programmable either as input or output. Input I/O lines are tri-stated and could be used with the on-board pull up or as tri-stated output. Each TTL I/O line has a pull resistor sourced by a common pull source. The pull voltage level is selectable to be either +3.3V, +5V and additionally GND.
16 of these ESD-protected TTL lines can be configured to be either a TTL interface or RS422 interface. Switching is done via the User FPGA. All 8 RS422 transceivers have individual internal switchable terminations.
The User FPGA is connected to a 512 Mbytes, 16 bit wide DDR3L SDRAM. (to be used with the AMD Memory Interface Generator)
For customer specific I/O extension or inter-board communication, the TXMC637 provides 64 FPGA I/Os on P14 (directly connected) and 4 FPGA Multi-Gigabit-Transceivers on P16. All P14 I/O lines can be configured in accordance with 7-Series. Select I/O features e.g. as 64 single ended LVCMOS25 or as 32 differential LVDS25 interface.
The User FPGA is configured by a serial quad SPI flash. For full PCIe specification compliance, the AMD Tandem Configuration Feature can be required for FPGA configuration. AMD Tandem Methodologies “Tandem PROM” should be the favored Methodology. The SPI flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for (real-time) debugging of the FPGA design.
User applications for the TXMC637 with Artix™ 7 FPGA can be developed using the AMD Vivado™ design tool. TEWS offers a well-documented FPGA Board Reference Design. It includes a constraint file with all necessary pin assignments and basic timing constraints. The FPGA Board Reference Design covers the main functionalities of the board.
The TXMC637 is delivered with the FPGA Board Reference Design. The FPGA could be programmed via the on-board Board Configuration Controller (BCC). Programming via JTAG interface using an USB programmer is also possible. In accordance with the PCI specification and the buffering of PCI header data, the contents of the user FPGA can be changed during operation.
TEWS Technologies is an Elite Certified AMD Adaptive Computing Partner and offers FPGA Design and Integration services for all its FPGA solutions. The engineering team specializes in designing highly optimized FPGA designs and has extensive experience in minimizing FPGA gate usage. Having the FPGA custom designed according to the customer’s needs avoids overhead and delays leading to a reduction of costs for the customer.