The TQMC600 is a VITA 93.0 compatible single-width QMC offering a user programmable AMD Artix 7 7A50T FPGA.
Depending on the order option the TQMC600 offers 32 ESD-protected 5V-tolerant TTL lines or 16 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers or Multipoint-LVDS transceivers.
All I/O lines are individually programmable as input or output. TTL I/O lines can be set to high, low, or tristate. Differential I/O lines are terminated, EIA-422 / EIA-485 lines with 120 Ω, M-LVDS lines with 100 Ω.
The User FPGA is configured by a SPI flash. An in-circuit debugging option is available via the QMC’s JTAG interface for read back and real-time debugging of the FPGA design (using the Vivado ILA).
User applications for the TQMC600 with 7A50T FPGA can be developed using the design software Vivado Design Suite HL WebPACK Edition, which can be downloaded free of charge from www.xilinx.com.
TEWS offers a well-documented basic FPGA Example Application design. It includes a constraints file with all necessary pin assignments and basic timing constraints.
The example design covers the main functionalities of the TQMC600. It implements PCIe to register mapping and basic I/O. It comes as a Xilinx Vivado Design Suite project with source code and as a ready-to-download bit stream.
