TXMC633

Reconfigurable FPGA with TTL and Differential I/O

  • Standard XMC module
  • User configurable FPGA (Xilinx Spartan-6)
  • 128 Mbyte, 16 bit wide DDR3 SDRAM
  • 64 TTL I/O line
    or 32 differential I/O lines (EIA-422 / EIA485 compatible)
    or 32 differential I/O lines (M-LVDS)
    or 32 TTL I/O line and 16 differential I/O lines
  • I/O direction is individually programmable
  • On board termination resistors for differential I/O
  • Front panel I/O (HD68 SCSI-3 type connector) and rear I/O via P14 and P16

Product status: Not Recommended for New Designs

The TXMC633 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable XC6SLX45T-2 or XC6SLX100T-2 Spartan-6 FPGA.

The TXMC633-x0R has 64 ESD-protected TTL lines; the TXMC633-x1R provides 32 differential I/O lines using EIA 422 / EIA 485 compatible, ESD-protected line transceivers. The TXMC633-x2R provides 32 TTL and 16 differential I/Os. The TXMC633-x3R provides 32 differential I/O lines using Multipoint-LVDS Transceiver. The TXMC633-x4R provides 32 TTL and 16 differential I/O Multipoint-LVDS Transceiver.

For customer specific I/O extension or inter-board communication, the TXMC633-xx provides 64 FPGA I/Os on P14 and 3 FPGA Multi-Gigabit-Transceiver on P16. P14 I/O lines could be configured as 64 single ended LVCMOS33 or as 32 differential LVDS33 interface.

All I/O lines are individually programmable as input or output. Setting as input sets the I/O line to tri-state and could be used with on-board pull-up also as tri-stated output. Each TTL I/O line has a pull-resistor. The pull- voltage level is programmable to be either +3.3V, +5V and additionally GND. The differential RS485 I/O lines are terminated by 120ohms resistors and the differential MLVDS I/O lines are terminated by 100ohms resistors.

The User FPGA is connected to a 128 Mbytes, 16 bit wide DDR3 SDRAM. The SDRAM-interface uses a hardwired internal Memory Controller Block of the Spartan-6.

The User FPGA is configured by a platform SPI flash or via PCIe download. The flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx ChipScope).

The direct configuration via PCIe of the User FPGA is realized by the Configuration FPGA. Configuration data is programmed via 32 bit transfer register to the User FPGA ( Spartan6). Data source are XILINX ISE binary files ( .bit file or .bin file) which are generated by XILINX ISE Design Software. These binary files consist of header, preamble and configuration data. Only configuration data must be transferred. See also the XILINX User Guide (ug380) Spartan6 FPGA Configuration for more information about configuration details and configuration data file formats.

User applications for the TXMC633 with XC6SLX45T-2 FPGA can be developed using the design software ISE Project Navigator (ISE) and Embedded Development Kit (EDK). IDE versions are 14.7. Licenses for both design tools are required.

TEWS offers a well-documented basic FPGA Example Application design. It includes an .ucf file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TXMC633. It implements local Bus interface to local Bridge device, register mapping, DDR3 memory access and basic I/O. It comes as a Xilinx ISE project with source code and as a ready-to-download bit stream.

Mechanical Interface Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard); Standard single-width (149mm x 74mm)
Electrical Interface PCI Express x1 Link (Base Specification 1.1) compliant interface conforming to ANSI/VITA 42.3-2006 (XMC PCI Express Protocol Layer Standard)
PCI Express Switch PI7C9X2G404 (Pericom)
PCI Express to PCI Bridge XIO2001 (Texas Instruments)
PCI Express Endpoint Spartan-6 PCI Express Endpoint Block
User configurable FPGA TXMC633-1x: XC6SLX45T-2 (Xilinx)
TXMC633-2x: XC6SLX100T-2 (Xilinx)
SPI-Flash W25Q32BV (Winbond) 32 Mbit (contains TXMC633 FPGA Example) or compatible
Board Configuration FPGA LCMXO2-2000HC (Lattice)
DDR3 RAM MT41J64M16 (Micron) or  MT41K64M16 (Micron) 64 Meg x 16 Bit
Number of Channels TXMC633-x0: 64 ESD-protected TTL lines
TXMC633-x1: 32 differential I/O lines
TXMC633-x2: 32 TTL and 16 differential I/O lines
TXMC633-x3: 32 M-LVDS I/O lines
TXMC633-x4: 32 TTL and 16 M-LVDS I/O lines.
I/O Connectors Front I/O HD68 SCSI-3 type Connector (AMP 787082-7 or compatible)
PMC P14 I/O (64 pin Mezzanine Connector)
XMC P16 I/O (114 pin Mezzanine Connector)
Power Requirements Depends on FPGA design
With TXMC633 FPGA Example Design / without external load
Typical @ +5V VPWR
TXMC633-xx: 0.650A
Typical @ +512V VPWR
TXMC633-xx: 0.300A
Temperature Range Operating: -40 °C to +85 °C
Storage: -40 °C to +85 °C
MTBF 320 000 h
Humidity 5 – 95% non-condensing
Weight 130 g

PRODUCT VARIATIONS

TXMC633-10R

Reconfigurable FPGA with 64 TTL I/O

Spartan-6 FPGA (XC6SLX45T-2); 128 MB DDR3; 64 TTL I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P16

TXMC633-11R

Reconfigurable FPGA with 32 RS422 I/O

Spartan-6 FPGA (XC6SLX45T-2); 128 MB DDR3; 32 RS422 I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P16

TXMC633-12R

Reconfigurable FPGA with 32 TTL and 16 RS422 I/O

Spartan-6 FPGA (XC6SLX45T-2); 128 MB DDR3; 32 TTL and 16 RS422I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P16

TXMC633-13R

Reconfigurable FPGA with 32 M-LVDS I/O

Spartan-6 FPGA (XC6SLX45T-2); 128 MB DDR3; 32 M-LVDS I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P16

TXMC633-14R

Reconfigurable FPGA with 32 TTL and 16 M-LVDS I/O

Spartan-6 FPGA (XC6SLX45T-2); 128 MB DDR3; 32 TTL and 16 M-LVDS I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P16

TXMC633-20R

Reconfigurable FPGA with 64 TTL I/O

Spartan-6 FPGA (XC6SLX100T-2); 128 MB DDR3; 64 TTL I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P16

TXMC633-21R

Reconfigurable FPGA with 32 RS422 I/O

Spartan-6 FPGA (XC6SLX100T-2); 128 MB DDR3; 32 RS422 I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P16

TXMC633-22R

Reconfigurable FPGA with 32 TTL and 16 RS422 I/O

Spartan-6 FPGA (XC6SLX100T-2); 128 MB DDR3; 32 TTL and 16 RS422 I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P16

TXMC633-23R

Reconfigurable FPGA with 32 M-LVDS I/O

Spartan-6 FPGA (XC6SLX100T-2); 128 MB DDR3; 32 M-LVDS I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P16

TXMC633-24R

Reconfigurable FPGA with 32 TTL and 16 M-LVDS I/O

Spartan-6 FPGA (XC6SLX100T-2); 128 MB DDR3; 32 TTL and 16 M-LVDS I/O on HD68; 64 direct FPGA I/O on P14; 3 MGTs on P1632 TTL I/O and 16 M-LVDS

ACCESSORIES

HD68 / SCSI-3 Cable

HD68 / SCSI-3 Terminal Block

Cable Kit for Modules with HD68 / SCSI-3 Connector

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet

Data Sheet - Issue 1.0.3

User Manual

User Manual - Issue 1.0.4