Reconfigurable FPGA with Analog Input (16 bit), Analog Output (16 bit) and TTL I/O

  • Standard XMC module
  • User configurable FPGA (Xilinx Spartan-6)
  • 128 Mbyte, 16 bit wide DDR3 SDRAM
  • 48 TTL I/O line
    • I/O direction is individually programmable
    • ESD protected
  • 32 channels 16 bit ADC
    • Offering single-ended and differential mode
    • 7 individually selectable voltage input ranges (up to ±24.576 V)
    • Sampling rate up to 1 Msps
  • 8 channels 16 bit DAC
    • 3 selectable voltage output ranges (up to ±10.5263 V)
    • 10 μs conversion time
  • Front panel I/O (VHD100 – 0.8 mm pitch connector) and rear I/O via P14 and P16

Product status: Not Recommended for New Designs

The TXMC635 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable XC6SLX45T-2 or XC6SLX100T-2 Xilinx Spartan-6 FPGA.

48 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programmable as input or output. Setting as input sets the I/O line to tri-state and could be used with on-board pull up also as open drain output. Each TTL I/O line has a pull resistor. The pull voltage level is selectable to be either +3.3V, +5V and additionally GND.

8 channels of 16 bit analog outputs allow software selectable output voltage ranges of ±10V, ±10.2564V  or ±10.5263V. The output voltage range can be individually set per channel. The conversion time is at most 10 µs and the DAC outputs are routed via operational amplifier in order to protect DAC from damage.

32 ADC input channels can be software configured to operate in single-ended or differential mode with 16 input channels. Each of the 32 channels has a resolution of 16 bit and can work with up to 1 MSPS. The programmable gain amplifier is software configurable and allows a full-scale input voltage range of up to ±24.576V.

For customer specific I/O extension or inter-board communication, the TXMC635-xxR provides 64 FPGA I/Os lines on P14 and 3 FPGA Multi-Gigabit-Transceiver on P16. P14 I/O lines could be configured as 64 single ended LVCMOS33 or as 32 differential LVDS33 interface.

The User FPGA is connected to a 128 Mbytes, 16 bit wide DDR3 SDRAM. The SDRAM-interface uses a hardwired internal Memory Controller Block of the Spartan-6.

The User FPGA is configured by a platform SPI flash or via PCIe download. The flash device is in-system programmable.  An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx ChipScope).

The direct configuration via PCIe of the User FPGA is realized by the Configuration FPGA. Configuration data is programmed via 32 bit transfer register to the User FPGA (Spartan6). Data source are XILINX ISE binary files (.bit file or .bin file) which are generated by XILINX ISE Design Software. These binary files consist of header, preamble and configuration data. Only configuration data must be transferred. See also the XILINX User Guide (ug380) Spartan6 FPGA Configuration for more information about configuration details and configuration data file formats.

User applications for the TXMC635 with XC6SLX45T-2 FPGA can be developed using the design software ISE Project Navigator (ISE) and Embedded Development Kit (EDK). IDE versions are 14.7. Licenses for both design tools are required.

TEWS offers a well-documented basic FPGA Example Application design. It includes an .ucf file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TXMC635. It implements local bus interface to local bridge device, register mapping, DDR3 memory access and basic I/O. It comes as a Xilinx ISE project with source code and as a ready-to-download bit stream.

Mechanical Interface Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA 42.0-2008 (Auxiliary Standard); Standard single-width (149mm x 74mm)
Electrical Interface PCI Express x1 Link (Base Specification 1.1) compliant interface conforming to ANSI/VITA 42.3-2006 (XMC PCI Express Protocol Layer Standard)
PCI Express Switch PI7C9X2G404 (Pericom)
PCI Express to PCI Bridge XIO2001 (Texas Instruments)
PCI Express Endpoint Spartan-6 PCI Express Endpoint Block
User configurable FPGA TXMC635-10R: XC6SLX45T-2 (Xilinx)
TXMC635-20R: XC6SLX100T-2 (Xilinx)
SPI-Flash W25Q32BV (Winbond) 32 Mbit (contains TXMC635 FPGA Example) or compatible
Board Configuration FPGA LCMXO2-2000HC (Lattice)
DDR3 RAM MT41J64M16 (Micron) or  MT41K64M16 (Micron) 64 Meg x 16 Bit
ADC ADAS3022 (Analog Devices)
DAC AD5764R (Analog Devices)
Number of Digital I/O 48 ESD-protected TTL lines; TTL signaling voltage level
Number of analog Input 32 single ended; Wherein always two inputs can be combined as one differential.
Number of analog Output 8 single ended
Analog Input Voltage ±20.48V (default); different gains are programmable for each input channel
±0.64V up to ±24.576V
Analog Input Filter (typ.) 480 kHz (-3dB); 70 kHz (-0.1dB)
Analog Output Voltage ±10V (default)
I/O Connectors Front I/O 0.8mm Pitch Connector (Honda HDRA-EC100LFDT-SL+)
PMC P14 I/O (64 pin Mezzanine Connector)
XMC P16 I/O (114 pin Mezzanine Connector)
Power Requirements Depends on FPGA design
With TXMC635 FPGA Example Design / without external load
1.10A typical @ +5V VPWR
0.50A typical @ +12V VPWR
Temperature Range Operating: -40 °C to +85 °C
Storage: -40 °C to +85 °C
MTBF 259 000 h
Humidity 5 – 95% non-condensing
Weight 124 g



Reconfigurable FPGA with 32 Analog Input , 8 Analog Output and 48 TTL I/O

Spartan-6 FPGA (XC6SLX45T-2); 128 MB DDR3; 32 Analog Input (16 bit); 8 Analog Output (16 bit); 48 TTL Front I/O; 64 direct FPGA I/O on P14; 3 MGTs on P16


Reconfigurable FPGA with 32 Analog Input, 8 Analog Output and 48 TTL I/O

Spartan-6 FPGA (XC6SLX100T-2); 128 MB DDR3; 32 Analog Input (16 bit); 8 Analog Output (16 bit); 48 TTL Front I/O; 64 direct FPGA I/O on P14; 3 MGTs on P16


VHDCI-100 Cable, 1.2 m

HD50 / SCSI-2 Terminal Block

Cable Kit for Modules with VHDCI-100 Connector


Device Driver for Board Family with Reconfigurable FPGA

Data Sheet

Data Sheet - Issue 1.0.4

User Manual

User Manual - Issue 1.0.4