The TMPE623 is a standard full PCI Express Mini Card, providing a user programmable AMD Artix™ 7 FPGA.
Depending on the order option, the TMPE623 offers 26 ESD-protected 5V-tolerant TTL lines or 13 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers or Multipoint-LVDS transceivers.
All I/O lines are individually programmable as input or output. TTL I/O lines can be set to high, low, or tristate. Each TTL I/O line has a pull-resistor to a common programmable pull voltage that can be set so +3.3 V, +5 V and GND. Differential I/O lines are terminated, EIA-422 / EIA-485 lines with 120 ohms, M-LVDS lines with 100 ohms.
The I/O signals are accessible through a 30 pin Pico-Clasp latching connector.
The User FPGA is configured by a SPI flash. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx ChipScope). For direct JTAG access to the FPGA using the Xilinx Platform Cable USB, the TA308 Programming Kit is required.
User applications for the TMPE623 with XC7A50T-2 FPGA can be developed using the design software AMD Vivado™ WebPACK, which can be downloaded free of charge from www.amd.com.
TEWS offers a well-documented basic FPGA Example Application design. It includes an .xdc file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TMPE623. It implements local Bus interface to local Bridge device, register mapping and basic I/O. It comes as an AMD Vivado™ project with source code and as a ready-to-download bit stream.
The TMPE623 provides a basic heatsink to facilitate thermal management. The heatsink can be used to install additional cooling solutions like passive or active heatsinks or to provide a thermal connection to an enclosure.
||PCI Express Mini Card conforming to PCI Express Mini Card Electromechanical Specification, Revision 2.0
Card Type: Full-Mini Card (50.95 x 30 mm)
||PCI Express x1 Link conforming to PCI Express Base Specification, Revision 2.1
The TMPE623 does not support the USB interface
|User configurable FPGA
||XC7A50T-2 (AMD Artix™ 7)
||Macronix 128 Mbit SPI-Flash covered by the Vivado “mx25l12845g” device settings.
(contains TMPE623 FPGA Example)
|Digital I/O Channels
||TMPE623-10R: 26 ESD-protected 5 V-tolerant TTL lines
TMPE623-11R: 13 differential EIA-422 / EIA-485 lines
TMPE623-12R: 13 differential M-LVDS lines
|Digital I/O Transceiver
||TMPE623-10R: 74LVC2G241 (or compatible)
TMPE623-11R: 65HVD75D (or compatible)
TMPE623-12R: 65LVDM176D (or compatible)
||30 pol. Pico-Clasp latching connector
|Power Requirements 1)
||Depends on FPGA design
With TMPE623 FPGA Example Design running, without external load:
300 mA to 500 mA typical @ +3.3 Vaux
200 mA typical @ +1.5 V
||Storage: -40°C to +85°C
||1 200 000 h
||5 – 95% non-condensing
1) depends on variant, for further details see User Manual
Reconfigurable FPGA with 26 TTL I/O
AMD Artix™ 7 FPGA (XC7A50T); 26 TTL I/O; I/O via 30 pos. Pico-Clasp connector
Reconfigurable FPGA with 13 differential EIA-422/EIA-485 I/O
AMD Artix™ 7 FPGA (XC7A50T); 13 differential EIA-422/EIA-485 I/O; I/O via 30 pos. Pico-Clasp connector
Reconfigurable FPGA with 13 differential M-LVDS I/O
AMD Artix™ 7 FPGA (XC7A50T); 13 differential M-LVDS I/O; I/O via 30 pos. Pico-Clasp connector
Pico-Clasp Cable Harness, 500mm
Pico-Clasp Terminal Block
Cable Kit for Modules with XRS Debug Connector
Cable Kit for Modules with Pico-Clasp Connector
Device Driver for Board Family with Reconfigurable FPGA