TMPE623

Reconfigurable FPGA with Digital I/O PCIe Mini Card

  • Standard PCI Express Mini Card
  • User programmable FPGA (Xilinx Artix-7)
  • 26 TTL lines (5 V-tolerant)
    or 13 differential I/O lines (EIA-422 / EIA-485 compatible)
    or 13 differential Multipoint-LVDS lines
  • ESD-protected I/O lines
  • Each I/O line is individually configurable (e.g. direction)
  • 3 state TTL output (high, low, and tristate)
  • 3 TTL pull voltages (GND, 3.3 V, and 5 V)
  • Onboard termination for differential I/O lines
  • Provides a basic heatsink to facilitate thermal management

Product status: Active

The TMPE623 is a standard full PCI Express Mini Card, providing a user programmable Xilinx Artix-7 7A50T FPGA.

Depending on the order option the TMPE623 offers 26 ESD-protected 5V-tolerant TTL lines or 13 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers or Multipoint-LVDS transceivers.

All I/O lines are individually programmable as input or output. TTL I/O lines can be set to high, low, or tristate. Each TTL I/O line has a pull-resistor to a common programmable pull voltage that can be set so +3.3 V, +5 V and GND. Differential I/O lines are terminated, EIA-422 / EIA-485 lines with 120 ohms, M-LVDS lines with 100 ohms.

The I/O signals are accessible through a 30 pin Pico-Clasp latching connector.

The User FPGA is configured by a SPI flash. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx ChipScope). For direct JTAG access to the FPGA using the Xilinx Platform Cable USB, the TA308 Programming Kit is required.

User applications for the TMPE623 with XC7A50T-2 FPGA can be developed using the design software Vivado WebPACK which can be downloaded free of charge from www.xilinx.com.

TEWS offers a well-documented basic FPGA Example Application design. It includes an .xdc file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TMPE623. It implements local Bus interface to local Bridge device, register mapping and basic I/O. It comes as a Xilinx Vivado project with source code and as a ready-to-download bit stream.

The TMPE623 provides a basic heatsink to facilitate thermal management. The heatsink can be used to install additional cooling solutions like passive or active heatsinks or to provide a thermal connection to an enclosure.

Mechanical Interface PCI Express Mini Card conforming to PCI Express Mini Card Electromechanical Specification, Revision 2.0
Card Type: Full-Mini Card (50.95 x 30 mm)
Electrical Interface PCI Express x1 Link conforming to PCI Express Base Specification, Revision 2.0
The TMPE623 does not support the USB interface
User configurable FPGA XC7A50T-2 (Xilinx)
SPI-Flash Macronix 128 Mbit SPI-Flash covered by the Vivado “mx25l12845g” device settings.
(contains TMPE623 FPGA Example)
Digital I/O Channels TMPE623-10R: 26 ESD-protected 5 V-tolerant TTL lines
TMPE623-11R: 13 differential EIA-422 / EIA-485 lines
TMPE623-12R: 13 differential M-LVDS lines
Digital I/O Transceiver TMPE623-10R: 74LVC2G241 (or compatible)
TMPE623-11R: 65HVD75D (or compatible)
TMPE623-12R: 65LVDM176D (or compatible)
I/O Connectors 30 pol. Pico-Clasp latching connector
Power Requirements 1) Depends on FPGA design
With TMPE623 FPGA Example Design running, without external load:
300 mA to 500 mA typical @ +3.3 Vaux
200 mA typical @ +1.5 V
Temperature Range Storage: -40°C to +85°C
MTBF 1 200 000 h
Humidity 5 – 95% non-condensing
Weight 13 g

1) depends on variant, for further details see User Manual

PRODUCT VARIATIONS

TMPE623-10R

Reconfigurable FPGA with 26 TTL I/O

Artix-7 FPGA (XC7A50T); 26 TTL I/O; I/O via 30 pos. Pico-Clasp connector

TMPE623-11R

Reconfigurable FPGA with 13 differential EIA-422/EIA-485 I/O

Artix-7 FPGA (XC7A50T); 13 differential EIA-422/EIA-485 I/O; I/O via 30 pos. Pico-Clasp connector

TMPE623-12R

Reconfigurable FPGA with 13 differential M-LVDS I/O

Artix-7 FPGA (XC7A50T); 13 differential M-LVDS I/O; I/O via 30 pos. Pico-Clasp connector

ACCESSORIES

Pico-Clasp Cable Harness, 500mm

Pico-Clasp Terminal Block

Cable Kit for Modules with XRS Debug Connector

Cable Kit for Modules with Pico-Clasp Connector

SOFTWARE

Device Driver for Board Family with Reconfigurable FPGA

Data Sheet

Data Sheet - Issue 1.0.0

User Manual

User Manual - Issue 1.0.4

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